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Wide-Band Data Converters cluster

LogoWideBandCluster

 

Welcome

The Wide-Band Data Converters cluster is part of the IC group of the Eindhoven University of Technology (TU/e). We investigate the speed-linearity performance boundaries of Analog-to-Digital and Digital-to-Analog conversion, while also educating students to do this. We want to be part of the cutting-edge technological developments in the GHz-range IC applications. Those in automotive and aerospace areas are particularly interesting for us, e.g. wireless communication, mm-wave radars. We always aim at unlocking new technologies and making our findings availble to the society.

Cluster Activity

Education

The Wide-Band Data Converters cluster actively participates in the education process of TU/e. Our cluster is responsible for one of the massive Bachelor courses of the Electrical Engineering faculty - the Electronic Circuits 2 (5ECC0), about 250 students annually. This course covers four main areas: Oscillators, Amplifiers, Digital Circuits and Data Converters. At the end of the Bachelor phase, we provide final (BEP) project possibilities to the students. Our main focus at that stage is layout physical design of circuits for high-speed data converters, e.g. comparators, amplifiers, digital gates, in advanced CMOS technologies, like 40nm and 28nm. In the Master education phase, our cluster is involved in the following courses: Semiconductor Physics and Materials, Advanced CMOS desgin and Data Converters 2: Design. In the course Semiconductor Physics and Materials, we give the physical fundamentals of diodes, mosfets and the CMOS IC manufacturing process. Students need this basis in order to understand important design considerations like short channel effects, mismatch, process corners, noise, etc. We put this knowledge in practice via projects in the Advanced CMOS design course. Further, we train students how to design sophisticated DAC and ADC circuits in the course Data Converters 2: Design and we prepare them for their Master internship and final projects. All our education activities are closely related to our research.

Research

The Wide-Band Data Converters cluster concentrates on three main areas of research: GH-range Digital-to-Analog conversion (D/A), GHz-range Analog-to-Digital Conversion (A/D) and a set of important aspects related to the Space-Time dimensions (synchronisation, signal alignment, phased-arrays).  Our D/A research covers the stand-alone Digital-to-Analog function, its extension towards the mixing-function in a common block Mixing-DAC and its extension along the space-time dimensions into a phased-array of D/A conversion units for digital beam forming and multi-beam transmission. Our A/D research covers Nyquist ADC, Sigma-Delta ADC and their extensions along the space-time dimensions into a phased-array of A/D conversion units for digital beam forming and multi-beam reception. The focus of our Sigma-Delta research is on continuous-time modulation for both low-pass and band-pass converters. At the moment, we concentrate, together with our industrial partners, on two main application areas: automotive and aerospace.

Why high speed wireless?

The picture below is taken from an autumn vacation of an average European family. Electronics is overall around us. Electronics is important for our lives. The picture shows the interior of a car in an usual trip of several hours. We heavily rely on a car radar for an adaptive cruise control, keyless and secure access, satellite navigation, etc. Moreover, we want to stay always connected and at highest possible data-rates, provided by the current 4G mobile standard.

AutomotiveMotivation

However, we believe in the Wide-Band Data Converters cluster that wireless data-rates should be made much higher and much more robust than what is available today, while their costs must be significantly reduced. The available IC technologies are sufficiently advanced in order to support this vision of ours. However, circuit and system solutions are needed! That is why we concentrate our efforts in areas like architecture and component-level innovation, integration of functions, phased-array, multi-beam wireless communication and others in order to discover and investigate the needed solutions.

Why in Space, too?

We recognize that parts of the needed solutions lie beyond local. These are in the global approaches. For example, permanent monitoring of Earth's water and air streams would provide key information to save fuel and time in transportation. Global monitoring can also issue early warnings for natural cataclysms and give time to people to escape. 

Intro Satellite Array
 

 

What are the speed-linearity limits of data converters?

Based on the Shannon–Hartley theorem, we know that to get higher communication channel capacity, we need to widen the communication bandwidth as much as possible. We need wide-band data converters! In practice, the communication bandwidth is regulated, since the medium is common. The air is for everyone and there are many parties who want to do wireless communication. Therefore, service providers need to buy a license in order to utilize a given RF band for communication and they are not allowed to transmit any electromagnetic waves above specified power outside their assigned licensed band.

High Performance Wireless
To maximize the communication the utilization of a given RF band, i.e. to increase the spectrum efficiency of our communication, we concentrate our research towards two main directions: increasing the linearity/reducing the noise and enabling multi-beam communication through digital beam-forming.

More linear D/A data converters, for example, not increase the useful dynamic range but also optimally make use of the assigned bandwidth. Non-linearity causes spectral regrowth at the two sides of a wide-band signal due to IM3, IM5, etc. effects. The larger the non-linearity, the more the regrowth. In such cases, the transmitter will have to reduce the effective signal bandwidth in order to comply with the spectral mask requirement. We do not want this, because this will reduce the channel capacity. We want to design highly linear D/A converters that maximally reduce the spectral regrowth by limiting the odd-order inter-modulation products.

This is of course very challenging, since wide-signal bandwidth data converters requires high sampling rates, which basically means high-speed circuits. Generally, linear data converters at high speeds is a contradicting trade-off. It is a difficult trade-off, which we, in the Wide-Band Data Converters cluster, love to solve!

Transmitter chain

Transmitting signals nowadays is easy. But transmitting wide-band signals in a power efficient way is a challenge.


For signal transmission basically a D/A converter, a mixer, a power amplifier, an antenna and a few filters around are needed. If we aim to transmit in high RF and wide-band with high linearity than the building components need to have low non-linear errors which sometimes can be achieved with high power consumption but sometimes it may not be possible at all. The efficiency of the PA is critical because usually it is the block that burns most of the power. To linearize it we can use digital per-distortion. This is a very effective method but it requires high linearity in all blocks preceding the PA, i.e. very linear DAC and a mixer. The challenges lie not only in the components themselves but also in the interface between the DAC and the mixer. That place can be a major source of non-linearity. A solution that we actively research in our Wide-Band Data Converters cluster is to combine the DAC and the Mixer function into a common block - the Mixing DAC.
Intro Transmitter Wireless

Efficient DA conversion for 5G Phased Array links

To maximize the transmission data rate, we need to use wide-signal bandwidth. In the regulated spectrum on Earth, such wide bands are available at high RF frequencies (mm-waves). However, the free-path loss of mm-waves considerably attenuates the signals. An efficient way to compensate the attenuation is to use phased-delay arrays and beam the electro-magnetic wave only at the target direction. This approach increases the effectively the total antenna gain of the system. Moreover, there are other advantages, too.
Intro Efficient DA Phased Array
Intro Phased Array Beaming The large transmission power is distributed among units and it is not required to be concentrated in a single place, which allows for finding an optimal power and linearity point for each parallel slice. However, one of the major advantages is the multi-beam possibilities that the digital beam forming allows. Multi-beam communication allows links with multiple users at same time and in the same frequency spectrum. This considerably improves the spectrum efficiency of the communication. However, such an approach is possible in practice if the whole chain "DAC-Mixer-PA-Antenna" is parallelized in an array. In order to enable digital beam forming, we need a lot of parallel data converters and each of them must be power efficient and small in size!

How far have we pushed so far the DAC signal bandwidth?

We built and measured in 2013 a 7GSps 6b DAC in 28nm CMOS. In this project, we not only explored a new for its time IC CMOS process but also targeted the smallest possible footprint with the idea to eventually use many of these in an array. However, the main target was of course to push the signal bandwidth as much as possible and still get SFDR>50dB for signals up to 1 GHz. Subsequently, a new problem arises: How can we measure such high speed data converters?
TCAS2 DAC 28nm  
The evolution of the CMOS technologies makes the price of a single transistor ever more affordable. We can today co-integrate redundant functions which facilitate the measurements, for example. Such circuits are made only for the purpose of testing. In this test-chip, we integrated a test clock source and a test 5K memory to store the digital input data. In this way, the only high speed signals that we needed to propagate on the test PCB were the two DAC differential outputs (BW=3.5GHz).

Classification of all options for combining D/A and Mixing functions

Published in Springer Analog Integrated Circuits and Signal Processing in December 2015.

Intro Mixed Signal Options  

Architecture: local mixing

Published via the PhD thesis of Elbert Behthum in 2015 "Wide-band mixing-DACs with high spectral purity" .

Intro Architecutre  

Architecture: output stage

Intro Output Stage  

System die photo

Intro MixingDAC System DIE Photo  

Measurements: dual-tone input

Intro MixingDAC Dual Tone Measurements  

Measurements: vs. output frequency

Intro MixingDAC Vs Output Frequency Measurements  

A 65nm CMOS 5.3 GHz 16b 1.75 GSps Mixing-DAC, IMD<-82dBc up to 1.9GHz

Intro MixingDAC ISSCC JSSC  

40nm self-calibrated CMOS 1GSps 16x12b DACs

This work explored how to build a very small area 12b 1GSps self-calibrated current-steering DAC (cell occupying just 0.037mm²), while delivering SFDR>60dB up to 200MHz and IM3<-60dB up to 350MHz. The DAC architecture, self-calibration apparatus and layout are specifically designed as a balance between small area, robustness, and high performance, so that embedding in a phased array can become feasible. The work has been published in the book "Smart and flexible digital-to-analog converters" in Springer 2011.
Intro 16x40nmDACs
Next to phased-array transmitters with digital beam forming capabilities, there is a strong trend towards increased integration of high-performance data converter together with large VLSI in small geometry CMOS processes. The main motivation is to be able to service the large amount of on-board digital real-estate without having to carry the overhead of high power dissipation, large board area and BOM costs associated with chip to chip interconnect. An aim of this work was to provide a solution for a high-performance very small area DAC that can be co-integrated with digital VLSI in nanometer scale CMOS. We also use this project as a platform to explore the challenges of massive integration of parallel DACs for digital beam forming phased array architectures.

The DAC interface needed to be included in the digital VLSI I/O block for external interfacing and hence it was preferable for it to be composed of thick-oxide transistors associated with the I/O block. In the proposed test chip, 16 12b DAC cells are implemented for multiple I/O. The DACs are created as modular repeatable units that are area-efficient, low power, and can be combined together in different ways. A problem is that small area, thick-oxide transistors and high performance contradict each other. Note that high-performance 12b DACs usually rely on 6-6 segmentation, resulting in an excellent dynamic performance thanks to the good matching of the 63 unary cells. However, this also results in very large silicon areas. In contrast, the proposed approach is to start from an area efficient low level of segmentation and subsequently solve the inherent problem of poorer matching and lower linearity by calibration. A very small (0.037mm²) 12b 1GSps DAC cell that uses segmentation of just 4 MSB unary and 8 LSB binary has been realized in 40nm CMOS. The DAC delivers comparable performance to state-of-the-art 12b stand-alone solutions while occupying a magnitude less silicon area, even though its core blocks are realized entirely with 280nm thick oxide I/O transistors. To save area, the DAC is designed for low intrinsic accuracy of about 8 bits, which keeps the area of its array of current sources small and compact (0.0075mm²), yielding a side-advantage of small parasitic gate and interconnect capacitances. The DAC calibrates out its errors, to give an improvement in accuracy of about 3 bits. The correction scheme choice is also driven by area efficiency. The recently published methods of MSB thermometer data scrambling and error mapping are not applicable here, since these need large unary segmentation. A self-calibration method is chosen that corrects the current errors by injecting corrections, from small calibrating DACs (CALDACs), at the drain of the current source transistors. This method is independent of the chosen DAC architecture and transistor intrinsic matching since it can calibrate both unary and binary current sources. The presented work extends it into an automatic correction of the DAC gain, followed by correction of all unary currents, and of the binary currents for bits 8, 7 and 6. All CALDACs occupy only 0.0092mm².
The CMOS digital part is implemented with thin oxide transistors. It comprises a 4-to-15 binary-to-thermometer decoder and the data synchronization latches. These blocks are the main source of digital disturbances. Hence, these are isolated inside the digital substrate, while the rest of the DAC is inside the analog substrate, where only CML-based circuits are used to minimize supply related disturbance and limit the need for power supply decoupling. The level-shifters block is used to adapt the levels of the digital signals to those of the thick oxide circuits.
The thick-oxide unary switched current cell is implemented in layout as a long slice of just 3.99μm in width (except for the current sources, which are part of the array block). The transistor design of the unary current cell uses 4 times unit element approach. In this way, for the implementation of the binary bits 8 and 7, the same sub-units are used, preserving high dynamic performance.
The figures show the measured SFDR performance versus a single tone input frequency. SFDR>60dB is maintained up to 200MHz. Since this DAC is designed to be used as a single standard cell in a much larger block that can have many parallel converters, the DAC cell has also been measured while operating together with another parallel instance. Both DACs are stacked together and measured as a 13-bit DAC, yielding even better linearity up to 100MHz. Beyond that frequency, only a negligible loss of performance is measured.
Furthermore, the figures show IM3 measurements based on two tones with 1MHz offset. For frequencies up to 80MHz, IM3 is about -70dBc before calibration and around -82dBc after calibration (see fig. 5a,b). Beyond 80MHz, the dynamic errors dominate the DAC performance. However, the DAC cell maintains -60dBc IM3 bandwidth up to 350MHz. The power consumption is distributed as follows: digital thin-oxide part 20mW; biasing 2.5mW; level-shifters 25mW; data drivers 15mW; and DAC output current is 11mA (50Ω load) from 2.5V (27.5mW). Although CML circuits are used for their switching quietness, the DAC overall power consumption remains competitive thanks to the small unary currents segmentation part. The proposed DAC cell had by 2011 the smallest area, while its performance was topping the high-performance DACs.

 

How to calibrate binary currents?

The challenge of calibrating binary currents is that they are scaled down with respect to a reference. So how do you measure different currents and tune these to an exact portion of a reference?

We developed a method to both measure and calibrate all binary currents in a given DAC. It is published in the book "Smart and flexible digital-to-analog converters" in Springer 2011 and verified with two test chips: one in 180nm CMOS and another one in 40nm CMOS.

Intro Calibrate Binary Currents
To calibrate binary currents, we need two sets of binary DACs and a reference current Itemp. The reference current should be nominally two times bigger than the MSB binary current. For example, Itemp can be like the MSB uny currents in a segmented DAC architecture.

So, the idea is as follows: in phase A (steps 1 to 2) we calibrate the MSB currents of the two sets of binary DACs to become equal to each other; in phase B (step 3) we calibrate the MSB curnts to become an exact portion (in this case 50%) of the reference current, I temp.

Step 1: We have a current comparator. We compare Itemp vs MSB binary current from sub-DAC 1 and all the other binary currents from sub-DAC 1 and an LSB. We have one bit comparison result. Depending on it, we increment or decrement the MSB binary current from sub-DAC1. We do that until the comparator changes sign, which is an indication that the current on both sides of the comparator are about equal. So, at this point we know that MSB binary current from sub-DAC 1 is about equal to 50% of the reference Itemp and the errors that are in all the other binary currents from sub-DAC 1 and an LSB.

Step 2: We have a current comparator. We compare Itemp vs MSB binary current from sub-DAC 2 and all the other binary currents from sub-DAC 1 and an LSB. We have one bit comparison result. Depending on it, we increment or decrement the MSB binary current from sub-DAC2. We do that until the comparator changes sign, which is an indication that the current on both sides of the comparator are about equal. So, at this point we know that MSB binary current from sub-DAC 2 is about equal to 50% of the reference Itemp and the errors that are in all the other binary currents from sub-DAC 1 and an LSB.

Step 3: We have a current comparator. We compare Itemp vs MSB binary current from sub-DAC 1 and MSB binary current from sub-DAC 2. We have one bit comparison result. Depending on it, we increment or decrement the MSB binary current from both sub-DAC 1 and sub-DAC 2, simultaneously. We do that until the comparator changes sign, which is an indication that the current on both sides of the comparator are about equal. So, at this point we know that MSB binary current from sub-DAC 1 and 2 is about equal to 50% of the reference Itemp.

Steps 4, 5, and 6 calibrate the MSB-1 currents to 25% of the reference. The procedure is similar to steps 1, 2, and 3, but now we need to scale down Itemp by a factor of 2. To do this we use already calibrated MSB binary currents which is exactly 50% of the Itemp. So we subtract the calibrated binary MSB current from the reference Itemp.

Receiver chain

The traditional I-Q receiver is usually perceived as a very power efficient solution since only the front-end circuits operate at high-speeds. Beyond the mixer in the receiver path chain, all circuits operate at the base-band frequencies. However, the requirements for matching both I and Q paths may complicate the implementation and unexpectedly increase the power consumption. A trend is two bring the ADC as close as possible to the antenna and hence make digital the whole receiver. For example, a band-pass SDM ADC can digitize both I and Q bands and the data demodulation can take place in the digital domain.
Intro Reciever Wireless
In our Wide-Band Data Converters cluster, we are looking at both Nyquist and Continuous-Time Low-Pass Sigma-Delta Modulator (SDM) ADC solutions that can be used in the traditional receivers and Continuous-Time Band-Pass SDM that can directly digitize and RF or IF band.

Efficient AD Conversion for 5G Phased Array Links

To increase the communication data-rate, we need wide signal bands. In the allocation of the frequency spectrum, these wider signal bands are available at higher carrier frequencies. At the moment mm-wave frequencies, e.g. 26Ghz, 60GHz, 80GHz, attract special interest from our side. However, note that the free-path loss at these high frequencies becomes considerable. The answers to this problem, we see in two main directions: power-efficiency and spectrum efficiency.
A key approach towards improving the power-efficiency of the receiver is the phased-array approach. It realizes directivity of the signal reception, which is equivalent to increasing the antenna gain of the system, and hence effectively compensates for the free-path loss at mm-waves.
The beam-forming can take place in either analog (mixed signal) or digital domain, hence analog (hybrid) and digital beam-forming approaches. Among these approaches, all main interest is on these that can realize multi-beam communication. Multi-beam links make possible to simultaneously communicate with multiple parties both in the same frequency spectrum and in the same time slots. This will be, of course, great for the spectrum-efficiency of our communication.
Multi-beam phased-array systems are possible by both analog and digital beam-forming approaches. For analog beam-forming for example an analog complex-multiplying matrix (ACMM) can be used, like proposed in the PhD thesis of Johan van den Heuvel. However, in our cluster we concentrate our efforts in digital beam forming for lower noise, lower harmonic distortion at high speed. For digital beam-forming, we need multiple input digital streams for the beam forming algorithms. These need to be provided by multiple ADCs. Therefore, we are actively looking at arrays of ADCs that can provide the necessary data conversion for digital beam steering.
Intro Efficient AD Phased Array

A Digital Calibration Technique for Wide-Band CT ΣΔ MASH ADCs with Relaxed Filter Requirements

Chenming ISCAS2016  

Current-Mode Multi-Path Excess Loop Delay Compensation for GHz Sampling CT ΣΔ ADCs

Chenming ISCAS2017

A CT BP SDM ADC with 45dB SNDR and 500MHz BW at 2GHz fc in 40nm CMOS

Daan Thesis  

What is the time?

Intro Clock Alignment