Wide-Band Data Converters cluster




The Wide-Band Data Converters cluster is a research group within the IC (Integrated Circuits) group at the Eindhoven University of Technology (TU/e). Our focus is on exploring the limits of speed and linearity in Analog-to-Digital and Digital-to-Analog conversion, while also teaching students about these concepts. We are interested in the latest technological developments in the GHz range for IC applications in areas such as automotive, wireless communications, mm-wave radars and beamforming. Our goal is to advance new technologies and make our research available to the public.

Cluster Activity


The Wide-Band Data Converters cluster at the Eindhoven University of Technology (TU/e) is actively involved in the education process. We are responsible for one of the major Bachelor courses in the Electrical Engineering faculty, called Electronic Circuits 2 (5ECC0), which is taken by approximately 250 students each year. This course covers topics such as oscillators, amplifiers, digital circuits, and data converters. At the end of the Bachelor phase, we offer final project opportunities to students, with a focus on the application demonstrators in the lab. In the Master education phase, our cluster is involved in several courses, including Semiconductor Physics and Materials, Advanced CMOS Design, and Data Converters 2: Design. In the Semiconductor Physics and Materials course, we provide students with a foundational understanding of diodes, MOSFETs, and the CMOS IC manufacturing process, which is essential for considering important design factors such as short channel effects, mismatch, process corners, and noise. In the Advanced CMOS Design course, students put this knowledge into practice through weekly IC analog design assignments. In the Data Converters 2: Design course, we teach students how to design sophisticated DAC and ADC circuits and prepare them for their Master internships and final projects. All of our educational activities are closely linked to our research efforts. We currently define MSc projects using 28nm and 22nm IC CMOS technologies.


The Wide-Band Data Converters cluster conducts research in three main areas: GHz-range Digital-to-Analog conversion (D/A), GHz-range Analog-to-Digital Conversion (A/D), and emerging related applications and technologies, such as Artificial Intelligence (AI) circuits and systems, beamforming, mm-wave transmitters and receivers. Our D/A research involves the standalone Digital-to-Analog function, its extension to a mixing function in a Mixing-DAC block, its extension to Power-Amplifiers (PA), mm-wave I/Q modulators, and the associated extensions along the space dimensions to a phased-array of D/A conversion units for digital beam forming and multi-beam transmission. Our A/D research includes Nyquist ADC, Sigma-Delta ADC, and their extension along the space dimensions to a phased-array of A/D conversion units for digital beam forming and multi-beam reception. Our Sigma-Delta research focuses on continuous-time modulation for low-pass and band-pass converters, with a particular emphasis on a novel beam-forming Sigma-Delta Modulator. Currently, we are working with industrial partners to apply our research to two main application areas: automotive and wireless telecommunications.

Why high speed wireless?

The following picture shows the inside of a car during a typical European family vacation. Electronics plays a significant role in our daily lives, as seen in the use of a car radar for adaptive cruise control, keyless and secure access, and satellite navigation. We also rely on electronics to stay connected with high data rates, such as those provided by the 5G mobile standard. The picture illustrates the extent to which electronics are present in our daily lives, even during a long car trip.


At the Wide-Band Data Converters cluster, we believe that it is possible to significantly increase wireless data rates and improve their robustness while also reducing costs. The available IC technologies are advanced enough to support this vision, but what is needed are circuit and system solutions. That is why we focus our efforts on areas such as architecture and component-level innovation, integration of functions, phased-array, and multi-beam wireless communication, among others, in order to find and explore the necessary solutions. Our aim is to push the boundaries of what is currently possible in wireless communication and to discover new ways of improving data rates and reliability.


What are the speed-linearity limits of data converters?

According to the Shannon–Hartley theorem, in order to increase the capacity of a communication channel, it is necessary to widen the communication bandwidth as much as possible. To achieve this, we need wide-band data converters. However, in practice, the communication bandwidth is regulated because the medium (air) is shared by multiple parties who want to use it for wireless communication. Service providers must purchase a license to use a specific RF band for communication and are not allowed to transmit electromagnetic waves above a certain power outside of their assigned licensed band. This ensures that there is sufficient bandwidth available for all parties to use and minimizes interference.

High Performance Wireless

In order to maximize the utilization of a given RF band and increase the efficiency of our communication, our research at the Wide-Band Data Converters cluster focuses on two main areas: improving linearity and reducing noise, and enabling multi-beam communication through digital beam-forming.

For example, more linear D/A data converters not only increase the useful dynamic range, but also make better use of the assigned bandwidth. Non-linearity can cause spectral regrowth at the edges of a wide-band signal due to IM3, IM5, and other effects. The more non-linear the converter is, the more regrowth there will be. This can cause the transmitter to reduce the effective signal bandwidth in order to comply with the spectral mask requirement, which reduces the channel capacity. Our goal is to design highly linear D/A converters that minimally impact spectral regrowth by limiting odd-order inter-modulation products.

Achieving this is a challenging task, as wide-bandwidth data converters require high sampling rates, which translates to high-speed circuits. In general, linear data converters at high speeds are difficult to achieve due to conflicting trade-offs. However, this is exactly the kind of challenge that we, in the Wide-Band Data Converters cluster, are excited to tackle.

Transmitter chain

Transmitting signals is relatively straightforward, but transmitting wide-band signals in a power-efficient manner is a challenge.

To transmit signals, a D/A converter, a mixer, a power amplifier, an antenna, and some filters are typically required. If we want to transmit high RF and wide-band signals with high linearity, the components must have low non-linear errors. This can sometimes be achieved with high power consumption, but not always. The efficiency of the power amplifier (PA) is particularly important because it is usually the component that consumes the most power. One solution is to use digital pre-distortion to linearize the PA, but this requires high linearity in all components preceding the PA, including the DAC and mixer. Non-linearity at the interface between the DAC and mixer can also be a major source of problems. To address these challenges, we are actively researching a solution in our Wide-Band Data Converters cluster that involves combining the DAC and mixer functions into a single block, known as a Mixing DAC.

Intro Transmitter Wireless

Efficient DA conversion for 5G Phased Array links

To maximize the transmission data rate, we need to use wide-bandwidth signals. In the regulated spectrum on Earth, such wide bands are available at high RF frequencies, also known as mm-waves. However, the free-path loss of mm-waves significantly attenuates the signals. One way to compensate for this attenuation is to use phased-delay arrays to beam the electromagnetic wave in the direction of the target, which effectively increases the total antenna gain of the system. This approach has several additional advantages as well.
Intro Efficient DA Phased Array
Intro Phased Array Beaming One of the benefits of using phased-delay arrays is that the large transmission power can be distributed among units, rather than being concentrated in a single location. This allows each parallel slice to operate at an optimal power and linearity point. However, perhaps the most significant advantage is the ability to use multi-beam communication, which allows multiple users to connect at the same time and in the same frequency spectrum. This significantly improves the spectrum efficiency of the communication. In order to enable digital beam forming, it is necessary to parallelize the entire "DAC-Mixer-PA-Antenna" chain in an array, which requires a large number of parallel data converters that are power efficient and small in size.

How far have we pushed so far the DAC signal bandwidth?

We built and measured in 2013 a 7GSps 6b DAC in 28nm CMOS. In this project, our goal was not only to explore a new, state-of-the-art IC CMOS process, but also to achieve the smallest possible footprint with the idea of eventually using many of these in an array. However, the main focus was on increasing the signal bandwidth as much as possible while maintaining SFDR (Spurious Free Dynamic Range) of greater than 50dB for signals up to 1 GHz. One challenge that arose was how to measure such high-speed data converters accurately.
TCAS2 DAC 28nm  
As CMOS technologies continue to evolve, the cost of a single transistor continues to decrease, making it more affordable to integrate redundant functions for testing purposes. In this test chip, we included a test clock source and a test 5K memory to store the digital input data. By doing this, the only high-speed signals that needed to be propagated on the test PCB were the two DAC differential outputs (BW=3.5GHz). This allowed us to more easily test the performance of the data converters.

Classification of all options for combining D/A and Mixing functions

Published in Springer Analog Integrated Circuits and Signal Processing in December 2015.

Intro Mixed Signal Options  

Architecture: local mixing

Published via the PhD thesis of Elbert Behthum in 2015 "Wide-band mixing-DACs with high spectral purity" .

Intro Architecutre  

Architecture: output stage

Intro Output Stage  

System die photo

Intro MixingDAC System DIE Photo  

Measurements: dual-tone input

Intro MixingDAC Dual Tone Measurements  

Measurements: vs. output frequency

Intro MixingDAC Vs Output Frequency Measurements  

A 65nm CMOS 5.3 GHz 16b 1.75 GSps Mixing-DAC, IMD<-82dBc up to 1.9GHz

Intro MixingDAC ISSCC JSSC  

40nm self-calibrated CMOS 1GSps 16x12b DACs

This work explored how to build a very small area 12b 1GSps self-calibrated current-steering DAC (cell occupying just 0.037mm²), while delivering SFDR>60dB up to 200MHz and IM3<-60dB up to 350MHz. The DAC architecture, self-calibration apparatus and layout are specifically designed as a balance between small area, robustness, and high performance, so that embedding in a phased array can become feasible. The work has been published in the book "Smart and flexible digital-to-analog converters" in Springer 2011.
Intro 16x40nmDACs
In this project, we aimed to create a highly efficient and compact DAC (digital-to-analog converter) that can be integrated with other digital VLSI in small CMOS processes. This DAC is intended to be used in phased-array transmitters with digital beam forming capabilities and as part of the larger trend towards increased integration of high-performance data converters with large VLSI systems. By maximizing the integration of these components, we hope to reduce power dissipation, board area, and cost while still maintaining high performance. We focused on creating a DAC that is small in size and efficient, while also being able to handle the challenges of massive integration for use in digital beam forming phased array architectures.

The DAC interface needed to be included in the digital VLSI I/O block for external interfacing and hence it was preferable for it to be composed of thick-oxide transistors associated with the I/O block. In the proposed test chip, 16 12b DAC cells are implemented for multiple I/O. The DACs are created as modular repeatable units that are area-efficient, low power, and can be combined together in different ways. A problem is that small area, thick-oxide transistors and high performance contradict each other. Note that high-performance 12b DACs usually rely on 6-6 segmentation, resulting in an excellent dynamic performance thanks to the good matching of the 63 unary cells. However, this also results in very large silicon areas. In contrast, the proposed approach is to start from an area efficient low level of segmentation and subsequently solve the inherent problem of poorer matching and lower linearity by calibration. A very small (0.037mm²) 12b 1GSps DAC cell that uses segmentation of just 4 MSB unary and 8 LSB binary has been realized in 40nm CMOS. The DAC delivers comparable performance to state-of-the-art 12b stand-alone solutions while occupying a magnitude less silicon area, even though its core blocks are realized entirely with 280nm thick oxide I/O transistors. To save area, the DAC is designed for low intrinsic accuracy of about 8 bits, which keeps the area of its array of current sources small and compact (0.0075mm²), yielding a side-advantage of small parasitic gate and interconnect capacitances. The DAC calibrates out its errors, to give an improvement in accuracy of about 3 bits. The correction scheme choice is also driven by area efficiency. The recently published methods of MSB thermometer data scrambling and error mapping are not applicable here, since these need large unary segmentation. A self-calibration method is chosen that corrects the current errors by injecting corrections, from small calibrating DACs (CALDACs), at the drain of the current source transistors. This method is independent of the chosen DAC architecture and transistor intrinsic matching since it can calibrate both unary and binary current sources. The presented work extends it into an automatic correction of the DAC gain, followed by correction of all unary currents, and of the binary currents for bits 8, 7 and 6. All CALDACs occupy only 0.0092mm².
The CMOS digital part is implemented with thin oxide transistors. It comprises a 4-to-15 binary-to-thermometer decoder and the data synchronization latches. These blocks are the main source of digital disturbances. Hence, these are isolated inside the digital substrate, while the rest of the DAC is inside the analog substrate, where only CML-based circuits are used to minimize supply related disturbance and limit the need for power supply decoupling. The level-shifters block is used to adapt the levels of the digital signals to those of the thick oxide circuits.
The thick-oxide unary switched current cell is implemented in layout as a long slice of just 3.99μm in width (except for the current sources, which are part of the array block). The transistor design of the unary current cell uses 4 times unit element approach. In this way, for the implementation of the binary bits 8 and 7, the same sub-units are used, preserving high dynamic performance.
The figures show the measured SFDR performance versus a single tone input frequency. SFDR>60dB is maintained up to 200MHz. Since this DAC is designed to be used as a single standard cell in a much larger block that can have many parallel converters, the DAC cell has also been measured while operating together with another parallel instance. Both DACs are stacked together and measured as a 13-bit DAC, yielding even better linearity up to 100MHz. Beyond that frequency, only a negligible loss of performance is measured.
Furthermore, the figures show IM3 measurements based on two tones with 1MHz offset. For frequencies up to 80MHz, IM3 is about -70dBc before calibration and around -82dBc after calibration (see fig. 5a,b). Beyond 80MHz, the dynamic errors dominate the DAC performance. However, the DAC cell maintains -60dBc IM3 bandwidth up to 350MHz. The power consumption is distributed as follows: digital thin-oxide part 20mW; biasing 2.5mW; level-shifters 25mW; data drivers 15mW; and DAC output current is 11mA (50Ω load) from 2.5V (27.5mW). Although CML circuits are used for their switching quietness, the DAC overall power consumption remains competitive thanks to the small unary currents segmentation part. The proposed DAC cell had by 2011 the smallest area, while its performance was topping the high-performance DACs.


How to calibrate binary currents?

The challenge of calibrating binary currents is that they are scaled down with respect to a reference. So how do you measure different currents and tune these to an exact portion of a reference?

We developed a method to both measure and calibrate all binary currents in a given DAC. It is published in the book "Smart and flexible digital-to-analog converters" in Springer 2011 and verified with two test chips: one in 180nm CMOS and another one in 40nm CMOS.

Intro Calibrate Binary Currents
To calibrate binary currents, we need two sets of binary DACs and a reference current Itemp. The reference current should be nominally two times bigger than the MSB binary current. For example, Itemp can be like the MSB uny currents in a segmented DAC architecture.

So, the idea is as follows: in phase A (steps 1 to 2) we calibrate the MSB currents of the two sets of binary DACs to become equal to each other; in phase B (step 3) we calibrate the MSB curnts to become an exact portion (in this case 50%) of the reference current, I temp.

Step 1: We have a current comparator. We compare Itemp vs MSB binary current from sub-DAC 1 and all the other binary currents from sub-DAC 1 and an LSB. We have one bit comparison result. Depending on it, we increment or decrement the MSB binary current from sub-DAC1. We do that until the comparator changes sign, which is an indication that the current on both sides of the comparator are about equal. So, at this point we know that MSB binary current from sub-DAC 1 is about equal to 50% of the reference Itemp and the errors that are in all the other binary currents from sub-DAC 1 and an LSB.

Step 2: We have a current comparator. We compare Itemp vs MSB binary current from sub-DAC 2 and all the other binary currents from sub-DAC 1 and an LSB. We have one bit comparison result. Depending on it, we increment or decrement the MSB binary current from sub-DAC2. We do that until the comparator changes sign, which is an indication that the current on both sides of the comparator are about equal. So, at this point we know that MSB binary current from sub-DAC 2 is about equal to 50% of the reference Itemp and the errors that are in all the other binary currents from sub-DAC 1 and an LSB.

Step 3: We have a current comparator. We compare Itemp vs MSB binary current from sub-DAC 1 and MSB binary current from sub-DAC 2. We have one bit comparison result. Depending on it, we increment or decrement the MSB binary current from both sub-DAC 1 and sub-DAC 2, simultaneously. We do that until the comparator changes sign, which is an indication that the current on both sides of the comparator are about equal. So, at this point we know that MSB binary current from sub-DAC 1 and 2 is about equal to 50% of the reference Itemp.

Steps 4, 5, and 6 calibrate the MSB-1 currents to 25% of the reference. The procedure is similar to steps 1, 2, and 3, but now we need to scale down Itemp by a factor of 2. To do this we use already calibrated MSB binary currents which is exactly 50% of the Itemp. So we subtract the calibrated binary MSB current from the reference Itemp.

Receiver chain

The traditional I-Q receiver is usually perceived as a very power efficient solution since only the front-end circuits operate at high-speeds. Beyond the mixer in the receiver path chain, all circuits operate at the base-band frequencies. However, the requirements for matching both I and Q paths may complicate the implementation and unexpectedly increase the power consumption. A trend is two bring the ADC as close as possible to the antenna and hence make digital the whole receiver. For example, a band-pass SDM ADC can digitize both I and Q bands and the data demodulation can take place in the digital domain.
Intro Reciever Wireless
In our Wide-Band Data Converters cluster, we are looking at both Nyquist and Continuous-Time Low-Pass Sigma-Delta Modulator (SDM) ADC solutions that can be used in the traditional receivers and Continuous-Time Band-Pass SDM that can directly digitize and RF or IF band.

Efficient AD Conversion for 5G Phased Array Links

To increase the communication data-rate, we need wide signal bands. In the allocation of the frequency spectrum, these wider signal bands are available at higher carrier frequencies. At the moment mm-wave frequencies, e.g. 26Ghz, 60GHz, 80GHz, attract special interest from our side. However, note that the free-path loss at these high frequencies becomes considerable. The answers to this problem, we see in two main directions: power-efficiency and spectrum efficiency.
A key approach towards improving the power-efficiency of the receiver is the phased-array approach. It realizes directivity of the signal reception, which is equivalent to increasing the antenna gain of the system, and hence effectively compensates for the free-path loss at mm-waves.
The beam-forming can take place in either analog (mixed signal) or digital domain, hence analog (hybrid) and digital beam-forming approaches. Among these approaches, all main interest is on these that can realize multi-beam communication. Multi-beam links make possible to simultaneously communicate with multiple parties both in the same frequency spectrum and in the same time slots. This will be, of course, great for the spectrum-efficiency of our communication.
Multi-beam phased-array systems are possible by both analog and digital beam-forming approaches. For analog beam-forming for example an analog complex-multiplying matrix (ACMM) can be used, like proposed in the PhD thesis of Johan van den Heuvel. However, in our cluster we concentrate our efforts in digital beam forming for lower noise, lower harmonic distortion at high speed. For digital beam-forming, we need multiple input digital streams for the beam forming algorithms. These need to be provided by multiple ADCs. Therefore, we are actively looking at arrays of ADCs that can provide the necessary data conversion for digital beam steering.
Intro Efficient AD Phased Array

A Digital Calibration Technique for Wide-Band CT ΣΔ MASH ADCs with Relaxed Filter Requirements

Chenming ISCAS2016  

Current-Mode Multi-Path Excess Loop Delay Compensation for GHz Sampling CT ΣΔ ADCs

Chenming ISCAS2017

A CT BP SDM ADC with 45dB SNDR and 500MHz BW at 2GHz fc in 40nm CMOS

Daan Thesis  

Nanosat Megaswarm

We would like to enable interferometry in km-wavelengths for radio-astronomy via thousands of small nano-satellite receivers for observation of deep-space objects. Kilometer-range wavelength observation of the universe is like a locked window now. Our earth atmosphere and the signal requirements for huge size antennas limit the scope of the Earth-based observation. Therefore, we believe we should go to Space!

The antenna-size requirement can be meet by constructing a virtual antenna based on a large area array of receiver points. For this we aim at building an intelligent swarm of small nanosatellites that can cover a huge area and hence produce together accurate images of the kHz emissions of large deep space objects, like black holes and nebulae.

However, to achieve this goal we need first to solve many problems like independent swarm-level behavior, inter-node communication, localization and synchronization, etc. For these, we need people together with whom we can solve these problems.