Master papers

You can find here the final graduation papers of the students from our cluster. To download these, an IP from TU/e is required.


A 45 dB SNDR, 200 MHz 4th-Order CT-SDM with SAR-based Quantizer in 40nm CMOS

Schematic and layout design of a 5.8 mW 45 dB SNDR 225 MHz bandwidth CT-SDM

Low-Power Beamforming Sigma-Delta Modulator with Spatial Interferer Rejection in 40nm CMOS


Design of the Digital Data Path for a Spectral Complaint PMCW Radar Based on mmWave Mixing-DAC

Tx-to-Rx Spillover Cancellation in mm-Wave PMCW Radars based on T&H and C-DAC

Internship projects presented at IEEE ECCTD 2020

A novel analysis of the beam squinting in wideband phased array digital I/Q transmitters

Novel Baseband Analog Beamforming through Resistive DACs and Sigma Delta Modulators


A 4 mW, 2 GHz, 47 dB SNDR, 250 MHz BW CT Sigma-Delta Modulator

A Multi-bit CTSDM for 50 dB SNDR in 250 MHz BW with ELD Compensation through Summation Amplifier


A CT BP SDM ADC with 50dB SNDR and 500MHz BW at 2GHz fc in 40nm CMOS

Gyrator-Based Extension using Negative Capacitance for High-Speed Comparators

A 2-bit-per-cycle SAR-Based Quantizer for a 2 GHz, 50 dB SNDR, 250 MHz BW CTSDM


Analysis of an In-Tip Digital IVUS Receiver with emphasis on the anti-aliasing filter

A 2mW 76dB-SNDR 1MHz-BW 6th-Order Hybrid CT Bandpass Sigma-Delta ADC for Medical Applications

System level modelling and investigation of the Digital Wave Transmitter concept for sub-THz wireless communication

A 1.9 mW 250 MHz Bandwidth Continuous-Time Σ∆ Modulator for Ultra-Wideband Applications

A 2 GHz 0.98 mW 4-bit SAR-Based Quantizer with ELD Compensation in an UWB CT Σ∆ Modulator


High-linearity SAR ADCs  using 2C DACs

An ultra-wideband RF mixing-DAC targeting IMD3 < -50dBc up to 25 GHz

A low power 130nm CMOS inventor based gyrator-C bandpass filter

System level analysis and modelling of MRI receiver imperfections and their influence on image quality

Metastability Error Compensation System for High-speed Continuous Time ΣΔ ADCs


Feasibility study and conceptual design of a 12bit 800MS/s SAR ADC in 40nm CMOS


Design strategies for high-speed single-slice intrinsic 8-bit SAR ADCs in planar and FinFET technologies

Integrated output transformers for high bandwidth, high linearity RF-DAC applications


A pre-correction method for improved static linearity using parallel DACs