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ΣΔ ADC

The key research questions that we target here are:

1. How can we settle the trade-off between large sinal bandwidth and power-efficiency?

2. What are the key SDM architectural choices that increase signal bandwidth, maintain low powe consumption, while achieving a compatitive linearity to the Nyquist ADC?

 

Our key research hypotheses are:

1. SDM with low OSR;

2. Multi-bit SDM;

3. Power efficient quantizers.

Theses:

Broadband Continuous-Time MASH Sigma-Delta ADCs

Papers:

Analysis of the Inter-Stage Signal Leakage in Wide BW Low OSR and High DR CT MASH ΔΣM

Novel Baseband Analog Beamforming through Resistive DACs and Sigma Delta Modulators

A 1.9 mW 250 MHz Bandwidth Continuous-Time ΣΔ Modulator for Ultra-Wideband Applications

A 2 GHz 0.98 mW 4-bit SAR-based quantizer with ELD compensation in an UWB CT ΣΔ modulator

Current-mode multi-path excess loop delay compensation for GHz sampling CT ΣΔ ADCs

A digital calibration technique for wide-band CT MASH ΣΔ ADCs with relaxed filter requirements

New youtube video by Qilong Liu!

Schreier FOM calculator

Schreier FOM calculator